Overview

Overview

GDS workflow DRC workflow LVS workflow DOCS workflow

Who

Ardit Uka, Jonas Hilbich, Iver Abrahamsen & Simen Eilevstjønn

Why

Creating this module is part of the Analog Integrated Circuits course at NTNU. The goal is to create a basic temperature sensor and get it to tape out in the TinyTapeout project. Along the way we will learn about the analog design and layout required and gain practical experience working with the tools and understanding the design workflow.

How

This module was developed through four separate milestones, each building on the results of the previous one. A detailed explanation of each circuit can be found under the Schematic section when generating the docs.

Milestone 1 - The Bandgap Circuit.

The first step of the project involves designing a bandgap reference circuit. The bandgap is a component used for temperature sensing and voltage references in integrated circuits. This circuit generates two key outputs:

• V_CTAT (Complementary to Absolute Temperature voltage): This voltage decreases linearly as temperature increases.

• I_PTAT (Proportional to Absolute Temperature current): This current increases linearly with temperature.

The combination of V_CTAT and I_PTAT allows the system to produce a temperature-dependent signal with a controlled linear relationship. By feeding these outputs into a subsequent oscillator circuit, the temperature-induced changes in voltage and current modulate the oscillator frequency. This frequency can then be measured using a digital counter to accurately determine the temperature of the system

Observations from the simulation

• I_PTAT shows a decreasing trend with temperature (negative slope).
• V_CTAT increases with temperature (positive slope).
• Despite opposite slopes, both outputs maintain linearity which is important for temperature sensing.

To simulate the bandgap and view plots:

cd sim/BANDGAP/
make typical

This will display plots for I_PTAT, V_CTAT, and their errors.

Optional: If you do not wish to see the plots, open tran.py in the BANDGAP folder and set:

DO_PLOT = False

Milestone 2 - The Oscillator

The I_PTAT and V_CTAT from Milestone 1 are used to control the frequency of the oscillator clock. The change in frequency caused by the linear variation of I_PTAT and V_CTAT is how the temperature is measured. As the temperature changes, it affects I_PTAT and V_CTAT, which in turn changes the oscillator frequency. This frequency is fed into a counter (developed in Milestone 3). The counter value is then used to determine the temperature of the bandgap reference.

Observations from the simulation

The figure above is an illustration of the output of the oscillator circuit during transient simulation.

The simulations were run for temperatures -5, 0, 10, 25, 30, 40, 50, 60, 70 and 75 degrees Celsium. The resulting frequency curve is shown below.

To quantify the nonlinearity of the output frequencies, a regression fit was performed and the deviations from the straight line frequency relative to the full scale was plotted below.

This shows that the error from the straight line is between 0.5% and 2.5%.

The regression model and the r^2 correlation figure for both the typical, extreme test case and Monte Carlo simulations can be found on the results page.

The same page contains the power usage measurements. Average active current is currently slightly out of spec at 104 $\mu$A typical, 146 $\mu$A maximum. The leakage current is currently 19 nA typically, up to 266 nA maximum, way above the 1 nA specification.

The leakage current can possibly be attribtuted to the floating output node. This may be pulled to gnd to possibly reduce leakage. Further optimisations will be performed later.

To simulate the oscillator alone:

cd sim/OSCILLATOR
make typical
cicsim wave output_tran/tran_SchGtKttTtVt.raw 

In cicsim, select v(osc_temp_1V8) to see the output of the oscillator.

To simulate the whole system:

cd sim/LELO_GR02
make typical

Milestone 3 - The Measurement

With the oscillator from Milestone 2 and the bandgap from Milestone 1 implemented, the next step is to measure the oscillator frequency. The implemented temperature sensor only oscillates while the PWRUP signal remains high (1.8 V). To count the oscillations per system clock cycle, and thus measure the frequency, a circuit that controlls the PWRUP signal is required. This functionality will be implemented in Verilog.

The Counter (counter.v)

First, the clock cycles generated by the oscillator must be counted. To accomplish this, an 8-bit ripple counter is implemented in Verilog. The microarchitecture of the counter is shown above. The counter is parametrized to allow for easy arbitrary widths. It is designed to clamp to the maximum value instead of rolling over. This decision was made to have the sensor indicate overtemperature conditions instead of giving a false sense of security by indicating a low temperature.

The counter receives the oscillation signal from the temperature sensor as its clock input and increments its value by one for each clock cycle. For a given oscillation frequency and PVT (process, voltage, and temperature) variation, the counter will reach a specific number of clock cycles within a defined measurement period.

To reset the counter, a reset signal is applied, which forces the counter value to zero. This reset signal is controlled by the state machine.

You can find the implementation of the counter in rtl/counter.v and it’s accompanying testbench in rtl/counter_tb.v. Use make sim_counter in the rtl directory to run the automated tests and check out sim/LELO_GR02/sensor_tb_sim.vcd in your waveform viewer of choice to see the waveform produced by the testbench.

The Finite State Machine (fsm.v)

With the counter implemented as shown above, it is now possible to count the clock cycles from the temperature sensor. To control both the counter and the sensor signal, a finite state machine (FSM) is used.

Module Ports

Port Type	Name	Description	Connection
Input	clk	System clock (from Tiny Tapeout).	External signal
Input	rst_n	Active-low reset signal used to reset the entire FSM.	External signal (User)
Input	start_i	Starts the temperature measurement.	External signal (User)
Input	cnt_i	Counter value from the counter module.	Connected to counter’s output.
Output	pwrup_osc_o	Power-up signal used to turn on the analog temperature sensor.	Connected to PWRUP port on analog design.
Output	reset_cnt_o	Active-high signal that resets the counter.	Connected to counter’s reset.
Output	completed_o	Flag indicating that the measurement is finished and data is ready.	Use as needed.
Output	clk_cycles_o	Number of counted clock cycles.	Use as needed.

State Flow & Behavior

The state machine uses three states:

• Global Reset: At any time, pulling rst_n low will asynchronously reset the FSM back to the IDLE state.
• IDLE: The FSM rests here by default. It holds the counter in reset (reset_cnt_o = 1) and keeps the temperature sensor powered off (pwrup_osc_o = 0). It waits here until the user drives the start signal high. After a transistion from CAPTURE, the clk_cycles_o contains the last oscialltor count with it’s validity indicated by completed_o (1 means valid).
• CNT: Entered with a high start signal. The counter reset is released (reset_cnt_o = 0), and the temperature sensor is powered on (pwrup_osc_o = 1). After one clock cycle, it automatically transitions to CAPTURE. The counter counts the osciallations of the temperature sensor.
• CAPTURE: The FSM powers down the temperature sensor and propagates the counter value and a completed_o signal to the output in the next cycle. After one clock cycle, it automatically transitions back to the IDLE state.

Sensor (sensor.v)

The FSM and counter are combined in the sensor module. This module contains a reduced set of the in- and outputs as discussed above as well as an input for the oscillator signal (osc_i). The module also features two parameters:

• CNT_WIDTH: Sets the width of the counter in bits (default: 8). This parameter also exists in and is linked to the submodules for the counter and fsm.
• SYNC_START: This decides if a two flip-flop synchronizer is added in the module to synchronize the start_i signal into the digial logic’s clock domain (default: 0 (false)). If the synchronizer is added, the start signal is delayed by two clock cycles.

Milestone 4 - The Physical Design

What

What	Cell/Name
Schematic	design/LELO_GR02_SKY130A/LELO_GR02.sch
Schematic	design/LELO_GR02_SKY130A/BANDGAP.sch
Schematic	design/LELO_GR02_SKY130A/BANDGAP_OPAMP.sch
Schematic	design/LELO_GR02_SKY130A/BANDGAP_DIODE.sch
Schematic	design/LELO_GR02_SKY130A/OSCILLATOR.sch
Schematic	design/LELO_GR02_SKY130A/OSCILLATOR_OPAMP.sch
RTL	rtl/Counter.v
RTL	rtl/FSM.v

Signal interface

Signal	Direction	Domain	Description
VDD_1V8	Input	VDD_1V8	Main supply
OSC_TEMP_1V8	Output	VDD_1V8	Temperature dependent oscillation frequency
PWRUP_1V8	Input	VDD_1V8	Power up the circuit
VSS	Input	Ground

Key parameters

Parameter	Min	Typ	Max	Unit
Technology		Skywater 130 nm
AVDD	1.7	1.8	1.9	V
Temperature	-40	27	125	C

---

Install

Clone LELO_GR02_SKY130A

To install, do the following

python3 -m pip install cicconf
git clone --recursive https://github.com/analogicus/lelo_gr02_sky130a lelo_gr02_sky130a
cicconf --rundir ./ --config lelo_gr02_sky130a/config.yaml clone --https

---

Schematics

• Overview
• Who
• Why
• How
  • Milestone 1 - The Bandgap Circuit.
    • Observations from the simulation
    • To simulate the bandgap and view plots:
  • Milestone 2 - The Oscillator
    • Observations from the simulation
    • To simulate the oscillator alone:
    • To simulate the whole system:
  • Milestone 3 - The Measurement
    • The Counter (counter.v)
    • The Finite State Machine (fsm.v)
      • Module Ports
      • State Flow & Behavior
    • Sensor (sensor.v)
  • Milestone 4 - The Physical Design
• What
• Signal interface
• Key parameters
  • Install
• Clone LELO_GR02_SKY130A
  • Schematics
  • LELO_GR02_SKY130A
    • LELO_GR02
    • BANDGAP
    • BANDGAP_OPAMP
    • BANDGAP_DIODE
    • OSCILLATOR
    • OSCILLATOR_OPAMP
  • Simulations
  • LELO_GR02_SKY130A
    • LELO_GR02
      • Transient analysis (tran)
    • BANDGAP
      • Transient analysis (tran)
    • BANDGAP_OPAMP
    • BANDGAP_DIODE
    • OSCILLATOR
    • OSCILLATOR_OPAMP
  • Layout

LELO_GR02_SKY130A

LELO_GR02

This schematic shows the complete system, which consists of a bandgap reference and an oscillator. The bandgap produces a reference voltage and a bias current, which are fed into the oscillator. The oscillator generates a clock signal that is used to drive a counter.

[Image: SVG not converted]

BANDGAP

The schematic depicts a bandgap reference circuit, which provides a temperature-independent voltage reference by combining PTAT and CTAT signals.

The bandgap reference has four inputs and two outputs. The supply voltage VDD_1V8 provides a 1.8 V DC supply to the circuit, while VSS serves as the ground reference.

There are two power-up signals; PWRUP_B_1V8, a buffered non-inverted signal used to enable the NMOS transistor for power gating, and PWRUP_N_1V8, an inverted signal used to control the PMOS transistor for power gating. Power gating is implemented to reduce leakage current and overall power consumption when the circuit is not active.

The bandgap circuit generates two outputs: I_PTAT and V_CTAT. The I_PTAT output is a current that is proportional to absolute temperature (PTAT), while V_CTAT is a voltage complementary to absolute temperature (CTAT).

In this system, V_CTAT serves as a voltage reference for the oscillator, while I_PTAT is used to charge the oscillator’s capacitor. The capacitor’s charging and discharging cycles control the oscillator’s frequency, which varies linearly with temperature

[Image: SVG not converted]

BANDGAP_OPAMP

The operational amplifier used within the bandgap circuit is shown in the figure above. It consists of an NMOS differential input pair combined with a PMOS current mirror load to provide amplification. Below the differential stage, a simple NMOS current mirror is used as a current source. A 8 kOhm resistor generates the bias current required to properly drive the op-amp. Power gating for the op-amp is implemented using PMOS transistors located above the circuit. The circuit also consists of a source follower at the output, to increase the opamp gain.

[Image: SVG not converted]

BANDGAP_DIODE

Diodes implemented using NPN BJTs with an area ratio of 1:8.

[Image: SVG not converted]

OSCILLATOR

The oscillator is responsible for converting the V_CTAT and I_PTAT produced by the bandgap into a temperature-dependent frequency that can be further processed by digital logic.

To achieve this, a transistor is charged using the I_PTAT current until it reaches the voltage given by V_CTAT. The comparison is performed using an OTA. The output of this OTA drives an NMOS which discharges the capacitor.

Buffers are implemented to introduce a small delay between the NMOS gate and the OTA. This delay ensures that the capacitor has enough time to fully charge or discharge before the gate voltage switches. This prevents incomplete transitions and ensuring stable oscillation.

The oscillator serves as the clock signal for a D-FF. The inverted output !Q is fed back to the D input, causing the flip-flop to toggle between 1 and 0 on every clock cycle. The resulting output signal is then used as a counting signal for subsequent digital processing.

[Image: SVG not converted]

OSCILLATOR_OPAMP

The same circuit as the operational amplifier used in the bandgap reference, but put it in its own file.

[Image: SVG not converted]

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Simulations

• TOC

LELO_GR02_SKY130A

LELO_GR02

README.md: “b2f0fb4 Tue Mar 31 00:16:56 2026 +0200 “

TB_NCM

Transient analysis (tran)

Check transient operation

Name	Parameter	Description		Min	Typ	Max	Unit
Oscillation frequency, offset at zero celsius	freq_intercept		Spec	1.000	0.000	10.000	MHz
			Sch_typ		6.498
			Sch_etc	3.442	4.510	5.862
			Sch_3std	1.749	4.339	6.928
Oscillation frequency, increase per kelvin	freq_slope		Spec	0.005	0.000	0.050	MHz
			Sch_typ		-0.108
			Sch_etc	0.014	0.018	0.024
			Sch_3std	0.014	0.019	0.023
Oscillation frequency, Pearson correlation coefficient	freq_rvalue		Spec	0.950	1.000	1.050
			Sch_typ		-1.000
			Sch_etc	0.989	0.997	0.999
			Sch_3std	0.992	0.998	1.003
Maximum error from straight line, relative to full scale	freq_max_abs_err_per_fs		Spec	0.000	0.000	1.010
			Sch_typ		0.014
			Sch_etc	0.030	0.048	0.081
			Sch_3std	-0.005	0.038	0.081
Active current at 25 celsius	i_act_25		Spec	5.000	30.000	100.000	uA
			Sch_typ		93.605
			Sch_etc
			Sch_3std
Leakage current at 25 celsius	i_leak_25		Spec	0.100	1.000	1.000	nA
			Sch_typ		0.238
			Sch_etc
			Sch_3std

BANDGAP

README.md: “b2f0fb4 Tue Mar 31 00:16:56 2026 +0200 “

TB_NCM

Transient analysis (tran)

Check transient operation

Name	Parameter	Description		Min	Typ	Max	Unit
Current proportial to temperature, offset at zero celsius	iptat_intercept		Spec	10.000	0.000	200.000	uA
			Sch_typ		2.417
			Sch_etc	11.651	61.719	141.958
			Sch_3std	49.879	61.099	72.319
Current proportial to temperature, increase per kelvin	iptat_slope		Spec	0.100	0.000	0.900	uA/K
			Sch_typ		0.006
			Sch_etc	0.415	0.540	0.705
			Sch_3std	0.531	0.630	0.728
Current proportial to temperature, Pearson correlation coefficient	iptat_rvalue		Spec	0.950	1.000	1.050
			Sch_typ		1.000
			Sch_etc	0.984	0.992	1.000
			Sch_3std	0.987	0.989	0.992
Voltage complementary to temperature, offset at zero celsius	vctat_intercept		Spec	200.000	0.000	1200.000	mV
			Sch_typ		750.503
			Sch_etc	702.661	735.409	755.578
			Sch_3std	732.979	736.342	739.705
Voltage complementary to temperature, increase per kelvin	vctat_slope		Spec	0.500	0.000	2.000	mV/K
			Sch_typ		-1.767
			Sch_etc	1.070	1.257	1.324
			Sch_3std	1.196	1.251	1.307
Voltage complementary to temperature, Pearson correlation coefficient	vctat_rvalue		Spec	0.950	1.000	1.050
			Sch_typ		-1.000
			Sch_etc	0.984	0.989	0.993
			Sch_3std	0.986	0.988	0.991
Active current at 25 celsius	i_act_25		Spec	5.000	30.000	100.000	uA
			Sch_typ		52.167
			Sch_etc
			Sch_3std
Leakage current at 25 celsius	i_leak_25		Spec	0.100	1.000	1.000	nA
			Sch_typ		0.339
			Sch_etc
			Sch_3std

BANDGAP_OPAMP

BANDGAP_DIODE

OSCILLATOR

OSCILLATOR_OPAMP

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Layout

GDS

GLTF

3D Model